1. Field of the Invention
The present invention relates to a structure of and a method of manufacturing a power semiconductor device such as a diode which performs rectification by a PN junction formed on a semiconductor substrate, or a MOS field effect transistor (MOSFET) or an Insulated Gate Bipolar Transistor (IGBT) which controls a main current by applying voltage to a gate formed on a semiconductor substrate with interposition of an insulating film.
2. Description of the Background Art
A power semiconductor device is constituted by a cell region in which a current flows and a terminal region formed around the cell region to maintain a breakdown voltage. As a terminal region structure, for example, a RESURF (Reduced Surface Field) structure is adopted. In the RESURF structure, a breakdown voltage is maintained by extending a depletion layer by a RESURF layer when a reverse voltage is applied. Here, a thick insulating film is necessary on a surface of the RESURF layer, in order to maintain the breakdown voltage. Presence of this thick insulating film causes a large level difference on a substrate, which makes it difficult to perform a process in subsequent steps such as application of a resist in a photoengraving step. Thus, a method of burying an insulating film in a substrate has been proposed, for example, in Japanese Patent Application Laid-Open No. 2009-88385. According to Japanese Patent Application Laid-Open No. 2009-88385, after implantation for forming a RESURF layer is performed in a terminal region, a trench is formed and an insulating film is buried therein, and then an unnecessary part is planarized by chemical mechanical polishing (CMP), thereby forming a thick insulating film on the RESURF layer, so that occurrence of a level difference is suppressed.
In the conventional inventions, when the insulating film buried after the formation of the trench is planarized by the CMP, an end point of the planarization is not defined. For example, when a silicon oxide film is used as the insulating film, if the planarization using the CMP is stopped before the substrate is exposed so that the silicon oxide film on the substrate remains over an entire surface of a wafer, damage to the substrate due to over-polishing can be prevented, but a variation of the thickness of the silicon oxide film within a wafer plane or within a chip is large. If the variation of the thickness of the silicon oxide film causes color unevenness in a surface of the substrate, an abnormality check based on an external appearance is impossible. Moreover, in a subsequent step of forming an electrode in a cell region, it is necessary to remove the silicon oxide film in the cell region by wet/dry etching. Here, a problem arises that the controllability of the etching amount deteriorates due to the variation of the thickness of the silicon oxide film.
On the other hand, if the planarization using the CMP is performed until the surface of the substrate is exposed so that the silicon oxide film on the surface of the substrate is wholly removed over the entire surface of the wafer, the variation of the thickness of the silicon oxide film on the substrate does not occur, but damage to the substrate due to over-polishing occurs. Occurrence of the damage to the substrate leads to a deterioration of electrical characteristics, such as occurrence of current leakage from a surface to a back surface of the substrate.